DELTA MODULATION
AIM: To study the DELTA modulation & demodulation technique.
APPARATUS:DELTA modulation & demodulation Trainer kit,
Power chords,
20 MHz Dual trace CRO,
Power supply.
THEORY: The block diagram of the delta modulation is also known as linear delta
modulator.The signal m(t) is the analog input signal. While r(t) is a reconstructed signal which is
same as the quantized input signal with 1 bit delay. The signal r (t) tries to follow the input signal
m(t) with one bit period delay.
APPARATUS:DELTA modulation & demodulation Trainer kit,
Power chords,
20 MHz Dual trace CRO,
Power supply.
THEORY: The block diagram of the delta modulation is also known as linear delta
modulator.The signal m(t) is the analog input signal. While r(t) is a reconstructed signal which is
same as the quantized input signal with 1 bit delay. The signal r (t) tries to follow the input signal
m(t) with one bit period delay.
The process of encoding is as follows. The comparator compares the input signal m(t) > r(t) a logic 1 is generated at the output ofthe comparator, otherwise a logic 0 is generated.
The value of logic 1 or logic 0 turned as current to generate So(t), the delta modulated output.
This output So(t) is fed to the 8 bit binary up/down counter to control it’s count direction. Logic 1
at the mode control input increases the count valueby one and logic ‘0’ decrements the count
value by one. All the 8 outputs of the counter are given to DAC to reconstruct the original signal.
In essence the counter & decoder forms the delta modulator in the feedback loop of the comparator. Thus if the input signal is higher thanthe reconstructed signal the counter increments at each step so as to enable the DAC output to reach to the input signal values. Similarly if the input signal m(t) is lower than the reconstructed signal r(t), the counter decrements at each step, and the DAC output gets reduced to reach a value to thatThe process of encoding is as follows. The comparator compares the input signal m(t) and r(t). if m(t) > r(t) a logic 1 is generated at the output ofthe comparator, otherwise a logic 0 is generated. The value of logic 1 or logic 0 turned as ∆(t) is held for the bit duration by the sampled and hold current to generate So(t), the delta modulated output.
This output So(t) is fed to the 8 bit binary up/down counter to control it’s count direction. Logic 1
at the mode control input increases the count valueby one and logic ‘0’ decrements the count
ts of the counter are given to DAC to reconstruct the original signal.
In essence the counter & decoder forms the delta modulator in the feedback loop of the comparator. Thus if the input signal is higher thanthe reconstructed signal the counter s at each step so as to enable the DAC output to reach to the input signal values. Similarly if the input signal m(t) is lower than the reconstructed signal r(t), the counter decrements at each step, and the DAC output gets reduced to reach a value to that input signal m(t) and r(t). if m(t) > r(t) a logic 1 is generated at the output ofthe comparator, otherwise a logic 0 is generated. (t) is held for the bit duration by the sampled andhold (t) is fed to the 8 bit binary up/down counter to control it’s count direction. Logic 1
at the mode control input increases the count valueby one and logic ‘0’ decrements the count
ts of the counter are given to DAC to reconstruct the original signal. In essence the counter & decoder forms the delta modulator in the feedback loop of the comparator. Thus if the input signal is higher thanthe reconstructed signal the counter s at each step so as to enable the DAC output to reach to the input signal values. Similarly if the input signal m(t) is lower than the reconstructed signal r(t), the counter decrements at each step, and the DAC output gets reduced to reach a value to thatof m(t).
The value of logic 1 or logic 0 turned as current to generate So(t), the delta modulated output.
This output So(t) is fed to the 8 bit binary up/down counter to control it’s count direction. Logic 1
at the mode control input increases the count valueby one and logic ‘0’ decrements the count
value by one. All the 8 outputs of the counter are given to DAC to reconstruct the original signal.
In essence the counter & decoder forms the delta modulator in the feedback loop of the comparator. Thus if the input signal is higher thanthe reconstructed signal the counter increments at each step so as to enable the DAC output to reach to the input signal values. Similarly if the input signal m(t) is lower than the reconstructed signal r(t), the counter decrements at each step, and the DAC output gets reduced to reach a value to thatThe process of encoding is as follows. The comparator compares the input signal m(t) and r(t). if m(t) > r(t) a logic 1 is generated at the output ofthe comparator, otherwise a logic 0 is generated. The value of logic 1 or logic 0 turned as ∆(t) is held for the bit duration by the sampled and hold current to generate So(t), the delta modulated output.
This output So(t) is fed to the 8 bit binary up/down counter to control it’s count direction. Logic 1
at the mode control input increases the count valueby one and logic ‘0’ decrements the count
ts of the counter are given to DAC to reconstruct the original signal.
In essence the counter & decoder forms the delta modulator in the feedback loop of the comparator. Thus if the input signal is higher thanthe reconstructed signal the counter s at each step so as to enable the DAC output to reach to the input signal values. Similarly if the input signal m(t) is lower than the reconstructed signal r(t), the counter decrements at each step, and the DAC output gets reduced to reach a value to that input signal m(t) and r(t). if m(t) > r(t) a logic 1 is generated at the output ofthe comparator, otherwise a logic 0 is generated. (t) is held for the bit duration by the sampled andhold (t) is fed to the 8 bit binary up/down counter to control it’s count direction. Logic 1
at the mode control input increases the count valueby one and logic ‘0’ decrements the count
ts of the counter are given to DAC to reconstruct the original signal. In essence the counter & decoder forms the delta modulator in the feedback loop of the comparator. Thus if the input signal is higher thanthe reconstructed signal the counter s at each step so as to enable the DAC output to reach to the input signal values. Similarly if the input signal m(t) is lower than the reconstructed signal r(t), the counter decrements at each step, and the DAC output gets reduced to reach a value to thatof m(t).
The block diagram of Delta modulator is shown below. It works in the same way as it was in the
feedback loop of the Delta modulator. The received Delta modulated signal S mode control input (U/D) of the up/down counter. The counter is a 8 bit wide and counts in binary fashion. All the 8 outputs are connected to an 8 -bit DAC, which gives a quantized analog signal (stepped wave form). A low pass filter is used to smooth out the steps. A buffer amplifier provides the necessary drive capability to the output signal. Thus the digital modulated data is demodulated and reconstructed into an analog signal.
Although this process of Delta Modulation and demodulation is a simple and cost effective
method of coding, there will be poor approximation at starting build up and hunting at flat top
signals. Another limitation is delta modulation is‘slope overloading’ If the input signal
The block diagram of Delta modulator is shown below. It works in the same way as it was in the
feedback loop of the Delta modulator. The received Delta modulated signal S
mode control input (U/D) of the up/down counter. The counter is a 8 bit wide and counts in
binary fashion. All the 8 outputs are connected to an 8-bit DAC, which gives a quantized analog
signal (stepped wave form). A low pass filter is used to smooth out the steps. A buffer amplifier
ecessary drive capability to the output signal. Thus the digital modulated data is demodulated and reconstructed into an analog signal.
Although this process of Delta Modulation and demodulation is a simple and cost effective
ing, there will be poor approximation at starting build up and hunting at flat top signals. Another limitation is delta modulation is‘slope overloading’ If the input signal frequency is greater than the limiting value slope overloading occurs. In such a reproduction of the analog signal is not possible. A sinusoidal waveform of amplitude A & frequency f has a maximum slope of 2overloading is to be avoided then the following condition
S ≥2πfA/fs
where S quantization step size
fs-sampling frequency
f-signal frequency
feedback loop of the Delta modulator. The received Delta modulated signal S mode control input (U/D) of the up/down counter. The counter is a 8 bit wide and counts in binary fashion. All the 8 outputs are connected to an 8 -bit DAC, which gives a quantized analog signal (stepped wave form). A low pass filter is used to smooth out the steps. A buffer amplifier provides the necessary drive capability to the output signal. Thus the digital modulated data is demodulated and reconstructed into an analog signal.
Although this process of Delta Modulation and demodulation is a simple and cost effective
method of coding, there will be poor approximation at starting build up and hunting at flat top
signals. Another limitation is delta modulation is‘slope overloading’ If the input signal
The block diagram of Delta modulator is shown below. It works in the same way as it was in the
feedback loop of the Delta modulator. The received Delta modulated signal S
mode control input (U/D) of the up/down counter. The counter is a 8 bit wide and counts in
binary fashion. All the 8 outputs are connected to an 8-bit DAC, which gives a quantized analog
signal (stepped wave form). A low pass filter is used to smooth out the steps. A buffer amplifier
ecessary drive capability to the output signal. Thus the digital modulated data is demodulated and reconstructed into an analog signal.
Although this process of Delta Modulation and demodulation is a simple and cost effective
ing, there will be poor approximation at starting build up and hunting at flat top signals. Another limitation is delta modulation is‘slope overloading’ If the input signal frequency is greater than the limiting value slope overloading occurs. In such a reproduction of the analog signal is not possible. A sinusoidal waveform of amplitude A & frequency f has a maximum slope of 2overloading is to be avoided then the following condition
S ≥2πfA/fs
where S quantization step size
fs-sampling frequency
f-signal frequency
A-signal amplitude
BLOCK DIAGRAM:
PROCEDURE:
1) Connect the AC power supply to the trainer kit and switch it ON.
2) Connect the AF signal output to the CH-1 of CRO andclock signal to CH-2 of CRO and
observe them.
3) Connect the AF signal output to modulator input andclock output to clock input of delta
modulator and observe the delta modulated output onCRO with respect to clock output & AF signal O/P.
4) Observe the D/A output with respect to AF signal output on CRO.
5) Connect the modulator output to the demodulator input and observe the demodulated output wit respect to AF signal output.
6) Calculate the phase shift of the demodulated output.
7) Plot the respected waveforms on graph sheet.
2) Connect the AF signal output to the CH-1 of CRO andclock signal to CH-2 of CRO and
observe them.
3) Connect the AF signal output to modulator input andclock output to clock input of delta
modulator and observe the delta modulated output onCRO with respect to clock output & AF signal O/P.
4) Observe the D/A output with respect to AF signal output on CRO.
5) Connect the modulator output to the demodulator input and observe the demodulated output wit respect to AF signal output.
6) Calculate the phase shift of the demodulated output.
7) Plot the respected waveforms on graph sheet.
MODEL GRAPH:
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